Welcome to RAD-Gen’s Documentation
RAD-Gen is a tool for silicon area/timing/power implementation results of hard (ASIC) components, FPGA fabric circuitry, and circuit modeling of 3D devices/packaging. It is part of the greater RAD Flow, which is an open source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable accelerator devices (RADs). Hard blocks may be network on chips (NoCs), tensor accelerators, or memory macros. RAD-Gen leverages the UC Berkeley Hammer framework to enable a PDK & Tool agnostic ASIC flow.
RAD-Gen is made up of three subtools: ASIC-DSE, COFFE, and IC-3D.
RAD-Gen is under heavy development.
Quick Start
Tools Overview
For Developers
How to Cite
The following paper may be used as a general citation for RAD-Gen:
@inproceedings{rad-gen,
title = {{Into the Third Dimension: Architecture Exploration Tools for 3D Reconfigurable Acceleration Devices}},
author = {Boutros, Andrew and Mahmoudi, Fatemehsadat and Mohaghegh, Amin and More, Stephen and Betz, Vaughn},
booktitle = {IEEE International Conference on Field-Programmable Technology (FPT)},
year = {2023}
}