coffe package

Submodules

coffe.basic_subcircuits module

coffe.basic_subcircuits.RAM_tgate_generate(filename, use_finfet)

Generates the SPICE subcircuit for a transmission gate used in the RAM cell. Appends it to file ‘filename’.

coffe.basic_subcircuits.RAM_tgate_generate_lp(filename, use_finfet)

Generates the SPICE subcircuit for a transmission gate used in the RAM cell. Appends it to file ‘filename’.

coffe.basic_subcircuits.inverter_generate(filename, use_finfet, use_technology)

Generates the SPICE subcircuit for an inverter. Appends it to file ‘filename’.

coffe.basic_subcircuits.lvl_shifter_generate(filename, use_finfet)

Generates the SPICE subcircuit for a single stage of the conventional lvl shifter. Appends it to file ‘filename’.

coffe.basic_subcircuits.nand2_generate(filename, use_finfet)

Generates the SPICE subcircuit for a 2input nand gate. Appends it to file ‘filename’.

coffe.basic_subcircuits.nand2_generate_lp(filename, use_finfet)

Generates the SPICE subcircuit for a 2input nand gate. Appends it to file ‘filename’.

coffe.basic_subcircuits.nand3_generate(filename, use_finfet)

Generates the SPICE subcircuit for a 3input nand gate. Appends it to file ‘filename’.

coffe.basic_subcircuits.nand3_generate_lp(filename, use_finfet)

Generates the SPICE subcircuit for a 3input nand gate. Appends it to file ‘filename’.

coffe.basic_subcircuits.ptran_generate(filename, use_finfet)

Generates the SPICE subcircuit for a pass-transistor. Appends it to file ‘filename’.

coffe.basic_subcircuits.ptran_pmos_generate(filename, use_finfet)

Generates the SPICE subcircuit for a PMOS pass-transistor. Appends it to file ‘filename’.

coffe.basic_subcircuits.rest_generate(filename, use_finfet)

Generates the SPICE subcircuit for a level-restorer. Appends it to file ‘filename’.

coffe.basic_subcircuits.tgate_generate(filename, use_finfet)

Generates the SPICE subcircuit for a transmission gate. Appends it to file ‘filename’.

coffe.basic_subcircuits.tgate_generate_lp(filename, use_finfet)

Generates the SPICE subcircuit for a transmission gate. Appends it to file ‘filename’.

coffe.basic_subcircuits.wire_generate(filename)

Generates the SPICE subcircuit for a wire. Appends it to file ‘filename’.

coffe.ble module

coffe.carry_chain module

coffe.cb_mux module

coffe.circuit_baseclasses module

coffe.coffe module

coffe.constants module

coffe.cost module

coffe.cost.cost_function(area, delay, area_opt_weight, delay_opt_weight)

coffe.cost.get_eval_area(fpga_inst, opt_type: str, subcircuit=None, is_ram_component: bool = False, is_cc_component: bool = False)

Get area cost for current FPGA state

coffe.data_structs module

coffe.debug module

coffe.ff_subcircuits module

coffe.ff_subcircuits.generate_ptran_2_input_select_d_ff(spice_filename, use_finfet)

Generates a D Flip-Flop SPICE deck

coffe.ff_subcircuits.generate_ptran_d_ff(spice_filename, use_finfet)

Generates a D Flip-Flop SPICE deck

coffe.ff_subcircuits.generate_tgate_2_input_select_d_ff(spice_filename, use_finfet)

Generates a D Flip-Flop SPICE deck

coffe.ff_subcircuits.generate_tgate_d_ff(spice_filename, use_finfet)

Generates a D Flip-Flop SPICE deck

coffe.fpga module

coffe.gen_routing_loads module

coffe.hardblock module

coffe.load_subcircuits module

coffe.load_subcircuits.RAM_local_routing_load_generate(spice_filename, num_on, num_partial, num_off)

coffe.load_subcircuits.general_routing_load_generate(spice_filename: str, tile_sb_on: List[int], tile_sb_partial: List[int], tile_sb_off: List[int], tile_cb_on: List[int], tile_cb_partial: List[int], tile_cb_off: List[int], gen_r_wire: Dict[str, Any], sb_mux: Any) → List[str]

Generates a routing wire load SPICE deck

coffe.load_subcircuits.hb_local_routing_load_generate(spice_filename, num_on, num_partial, num_off, hb_name, mux_name)

coffe.load_subcircuits.local_routing_load_generate(spice_filename, num_on, num_partial, num_off)

coffe.logic_block module

coffe.lut module

coffe.lut_subcircuits module

coffe.lut_subcircuits.generate_carry_chain_perf_ripple(spice_filename: str, circuit_name: str, use_finfet: bool) → Tuple[List[str], List[str]]

Generates carry chain inverters for sum SPICE deck

coffe.lut_subcircuits.generate_carry_inter(spice_filename: str, circuit_name: str, use_finfet: bool) → Tuple[List[str], List[str]]

Generates the driver to load “cin” of the next cluster

coffe.lut_subcircuits.generate_full_adder(spice_filename: str, circuit_name: str, use_finfet: bool) → Tuple[List[str], List[str]]

Generates full adder SPICE deck

coffe.lut_subcircuits.generate_full_adder_simplified(spice_filename: str, circuit_name: str, use_finfet: bool) → Tuple[List[str], List[str]]

Generates full adder SPICE deck

coffe.lut_subcircuits.generate_ptran_lut4(spice_filename: str, min_tran_width: float, use_finfet: bool) → Tuple[List[str], List[str]]

Generates a 4LUT SPICE deck

coffe.lut_subcircuits.generate_ptran_lut5(spice_filename: str, min_tran_width: float, use_finfet: bool) → Tuple[List[str], List[str]]

Generates a 5LUT SPICE deck

coffe.lut_subcircuits.generate_ptran_lut6(spice_filename: str, min_tran_width: float, use_finfet: bool) → Tuple[List[str], List[str]]

Generates a 6LUT SPICE deck

coffe.lut_subcircuits.generate_ptran_lut_driver(spice_filename: str, lut_input_name: str, lut_input_type: str) → Tuple[List[str], List[str]]

Generate a pass-transistor LUT driver based on type.

coffe.lut_subcircuits.generate_ptran_lut_driver_load(spice_filename, lut_input_name, K, use_fluts)

Generates LUT input load SPICE deck Note: the input K incase of fluts is still input comming from the architecure file. For a 5-FLUT K = 5

coffe.lut_subcircuits.generate_ptran_lut_not_driver(spice_filename: str, lut_input_name: str) → Tuple[List[str], List[str]]

Generate a pass-transistor LUT driver based on type.

coffe.lut_subcircuits.generate_skip_and_tree(spice_filename, circuit_name, use_finfet, nand1_size, nand2_size)

Generates carry chain skip and tree for sum SPICE deck

coffe.lut_subcircuits.generate_tgate_lut4(spice_filename: str, min_tran_width: float, use_finfet: bool) → Tuple[List[str], List[str]]

Generates a 4LUT SPICE deck

coffe.lut_subcircuits.generate_tgate_lut5(spice_filename: str, min_tran_width: float, use_finfet: bool) → Tuple[List[str], List[str]]

Generates a 5LUT SPICE deck

coffe.lut_subcircuits.generate_tgate_lut6(spice_filename: str, min_tran_width: float, use_finfet: bool) → Tuple[List[str], List[str]]

Generates a 6LUT SPICE deck

coffe.lut_subcircuits.generate_tgate_lut_driver(spice_filename: str, lut_input_name: str, lut_input_type: str) → Tuple[List[str], List[str]]

Generate a pass-transistor LUT driver based on type.

coffe.lut_subcircuits.generate_tgate_lut_driver_load(spice_filename: str, lut_input_name: str, K: int, use_fluts: bool) → List[str]

Generates LUT input load SPICE deck

coffe.lut_subcircuits.generate_tgate_lut_not_driver(spice_filename: str, lut_input_name: str) → Tuple[List[str], List[str]]

Generate a pass-transistor LUT driver based on type.

coffe.memory_subcircuits module

coffe.memory_subcircuits.generate_columndecoder(spice_filename, circuit_name, decsize)

coffe.memory_subcircuits.generate_columndecoder_lp(spice_filename, circuit_name, decsize)

coffe.memory_subcircuits.generate_configurabledecoder2ii(spice_filename, nand2circuit_name)

coffe.memory_subcircuits.generate_configurabledecoder2ii_lp(spice_filename, nand2circuit_name)

coffe.memory_subcircuits.generate_configurabledecoder3ii(spice_filename, nand3circuit_name)

coffe.memory_subcircuits.generate_configurabledecoder3ii_lp(spice_filename, nand3circuit_name)

coffe.memory_subcircuits.generate_configurabledecoderi(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_configurabledecoderi_lp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_configurabledecoderiii(spice_filename: str, circuit_name: str, required_size: int) → Tuple[List[str], List[str]]

coffe.memory_subcircuits.generate_configurabledecoderiii_lp(spice_filename: str, circuit_name: str, required_size: int) → Tuple[List[str], List[str]]

coffe.memory_subcircuits.generate_level_shifter(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_memorycell(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_memorycell_lp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_mtj_cs_lp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_mtj_memorycell_high_lp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_mtj_memorycell_low_lp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_mtj_memorycell_reference_lp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_mtj_memorycell_reference_lp_target(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_mtj_memorycellh_reference_lp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_mtj_sa_lp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_mtj_writedriver_lp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_pgateoutputcrossbar(spice_filename: str, circuit_name: str, maxwidth: int, use_tgate: bool) → Tuple[List[str], List[str]]

coffe.memory_subcircuits.generate_precharge(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_precharge_lp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_rowdecoderstage0(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_rowdecoderstage0_lp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_rowdecoderstage1(spice_filename, circuit_name, nandtype)

coffe.memory_subcircuits.generate_rowdecoderstage1_lp(spice_filename, circuit_name, nandtype)

coffe.memory_subcircuits.generate_rowdecoderstage3(spice_filename, circuit_name, fan_out, number_of_banks)

coffe.memory_subcircuits.generate_rowdecoderstage3_lp(spice_filename, circuit_name, fan_out, number_of_banks)

coffe.memory_subcircuits.generate_samp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_samp_lp(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_wordline_driver(spice_filename, circuit_name, nand_size, repeater)

coffe.memory_subcircuits.generate_wordline_driver_lp(spice_filename, circuit_name, nand_size, repeater)

coffe.memory_subcircuits.generate_writedriver(spice_filename, circuit_name)

coffe.memory_subcircuits.generate_writedriver_lp(spice_filename, circuit_name)

coffe.mux module

coffe.mux_subcircuits module

coffe.mux_subcircuits.generate_dedicated_driver(spice_filename, driver_name, num_bufs, top_name)

Generate a driver for the dedicated routing links

coffe.mux_subcircuits.generate_ptran_2_to_1_mux(spice_filename, mux_name)

Generate a 2:1 pass-transistor MUX with shared SRAM

coffe.mux_subcircuits.generate_ptran_2lvl_mux(spice_filename, mux_name, implemented_mux_size, level1_size, level2_size)

Creates two-level MUX circuits There are 3 different types of MUX that are generated depending on how ‘on’ the mux is

1. Fully on (both levels are on) circuit name: mux_name + “_on”

2. Partially on (only level 1 is on) circuit name: mux_name + “_partial”

3. Off (both levels are off) circuit name: mux_name + “_off”

coffe.mux_subcircuits.generate_ptran_2lvl_mux_no_driver(spice_filename, mux_name, implemented_mux_size, level1_size, level2_size)

Creates two-level MUX files There are 3 different types of MUX that are generated depending on how ‘on’ the mux is

1. Fully on (both levels are on) circuit name: mux_name + “_on”

2. Partially on (only level 1 is on) circuit name: mux_name + “_partial”

3. Off (both levels are off) circuit name: mux_name + “_off”

No driver is attached to the on mux (we need this for the local routing mux)

coffe.mux_subcircuits.generate_tgate_2_to_1_mux(spice_filename, mux_name)

Generate a 2:1 pass-transistor MUX with shared SRAM

coffe.mux_subcircuits.generate_tgate_2lvl_mux(spice_filename, mux_name, implemented_mux_size, level1_size, level2_size)

Creates two-level MUX circuits There are 3 different types of MUX that are generated depending on how ‘on’ the mux is

1. Fully on (both levels are on) circuit name: mux_name + “_on”

2. Partially on (only level 1 is on) circuit name: mux_name + “_partial”

3. Off (both levels are off) circuit name: mux_name + “_off”

coffe.mux_subcircuits.generate_tgate_2lvl_mux_no_driver(spice_filename, mux_name, implemented_mux_size, level1_size, level2_size)

Creates two-level MUX files There are 3 different types of MUX that are generated depending on how ‘on’ the mux is

1. Fully on (both levels are on) circuit name: mux_name + “_on”

2. Partially on (only level 1 is on) circuit name: mux_name + “_partial”

3. Off (both levels are off) circuit name: mux_name + “_off”

No driver is attached to the on mux (we need this for the local routing mux)

coffe.new_ram module

coffe.parsing module

coffe.plotting module

coffe.ram module

coffe.sb_mux module

coffe.spice module

coffe.top_level module

coffe.top_level.generate_HB_local_mux_top(mux_name, name)

Generate the top level local mux SPICE file

coffe.top_level.generate_RAM_local_mux_top(mux_name)

Generate the top level local mux SPICE file

coffe.top_level.generate_RAM_local_mux_top_lp(mux_name)

Generate the top level local mux SPICE file

coffe.top_level.generate_columndecoder_top(name, numberoftgates, decsize)

coffe.top_level.generate_columndecoder_top_lp(name, numberoftgates, decsize)

coffe.top_level.generate_configurabledecoder2ii_top(name, fanout, size)

coffe.top_level.generate_configurabledecoder2ii_top_lp(name, fanout, size)

coffe.top_level.generate_configurabledecoderi_top(name, numberofgates2, numberofgates3, ConfiDecodersize)

coffe.top_level.generate_configurabledecoderi_top_lp(name, numberofgates2, numberofgates3, ConfiDecodersize)

coffe.top_level.generate_configurabledecoderiii_top(name, fanin1, fanin2, required_size, tgatecount)

coffe.top_level.generate_configurabledecoderiii_top_lp(name, fanin1, fanin2, required_size, tgatecount)

coffe.top_level.generate_dedicated_driver_top(name, top_name, num_bufs)

coffe.top_level.generate_flut_mux_top(name, use_tgate, enable_carry_chain, gen_r_wire: dict)

coffe.top_level.generate_general_ble_output_top(name, use_tgate, gen_r_wire: dict)

coffe.top_level.generate_local_ble_output_top(name, use_tgate, gen_r_wire: dict)

Generate the top level local ble output SPICE file

coffe.top_level.generate_lut4_top(lut_name, use_tgate)

Generate the top level 4-LUT SPICE file

coffe.top_level.generate_lut5_top(lut_name, use_tgate)

Generate the top level 5-LUT SPICE file

coffe.top_level.generate_lut6_top(lut_name, use_tgate)

Generate the top level 6-LUT SPICE file

coffe.top_level.generate_lut_and_driver_top(input_driver_name, input_driver_type, use_tgate, use_fluts)

Generate the top level lut with driver SPICE file. We use this to measure final delays of paths through the LUT.

coffe.top_level.generate_lut_driver_not_top(input_driver_name, input_driver_type)

Generate the top level lut input not driver SPICE file

coffe.top_level.generate_lut_driver_top(input_driver_name, input_driver_type)

Generate the top level lut input driver SPICE file

coffe.top_level.generate_mtj_charge(name, colsize)

coffe.top_level.generate_mtj_discharge(name, colsize)

coffe.top_level.generate_mtj_read_power_top_lp(name, mtj_per_column)

coffe.top_level.generate_mtj_sa_top(name, colsize)

coffe.top_level.generate_mtj_write_power_top_lp(name, mtj_per_column)

coffe.top_level.generate_pgateoutputcrossbar_top(name, maxwidth, def_use_tgate)

coffe.top_level.generate_precharge_top(name, numberofsrams)

coffe.top_level.generate_precharge_top_lp(name, numberofsrams)

coffe.top_level.generate_rowdecoderstage0_top(name, numberofgates2, numberofgates3, decodersize, label2, label3)

coffe.top_level.generate_rowdecoderstage0_top_lp(name, numberofgates2, numberofgates3, decodersize, label2, label3)

coffe.top_level.generate_rowdecoderstage1_top(name, fanout, size)

coffe.top_level.generate_rowdecoderstage1_top_lp(name, fanout, size)

coffe.top_level.generate_rowdecoderstage3_top(name, fanin1, fanin2, sramcount, number_of_banks, gate_type)

coffe.top_level.generate_rowdecoderstage3_top_lp(name, fanin1, fanin2, sramcount, number_of_banks, gate_type)

coffe.top_level.generate_samp_top(name, numberofsrams)

coffe.top_level.generate_samp_top_part1(name, numberofsrams, difference)

coffe.top_level.generate_samp_top_part1_lp(name, numberofsrams, difference)

coffe.top_level.generate_samp_top_part2(name, numberofsrams, difference)

coffe.top_level.generate_samp_top_part2_lp(name, numberofsrams, difference)

coffe.top_level.generate_sram_read_power_top(name, sram_per_column, unselected_column_count)

coffe.top_level.generate_sram_read_power_top_lp(name, sram_per_column, unselected_column_count)

coffe.top_level.generate_sram_writehh_power_top_lp(name, sram_per_column, unselected_column_count)

coffe.top_level.generate_sram_writelh_power_top_lp(name, sram_per_column, unselected_column_count)

coffe.top_level.generate_sram_writep_power_top_lp(name, sram_per_column, unselected_column_count)

coffe.top_level.generate_wordline_driver_top_lp(name, sramcount, nandsize, smallrow, repeater)

coffe.top_level.generate_writedriver_top(name, numberofsrams)

coffe.top_level.generate_writedriver_top_lp(name, numberofsrams)

coffe.tran_sizing module

coffe.utils module

coffe.utils.check_arch_params(arch_params, filename)

This function checks the architecture parameters to make sure that all the parameters specified are compatible with COFFE. Right now, this functions just checks really basic stuff like checking for negative values where there shoulnd’t be or making sure the LUT size is supported etc. But in the future I think it might be a good idea to make this checker a little more intelligent. For example, we might check things like Fc values that make no sense. Such as an Fc that is so small that you can’t connect to wires, or something like that.

coffe.utils.check_for_time()

This finction should be used before each call for HSPICE it checks if the time is between 2:30 a.m and 3:30 a.m. since during this time it was found that the license doesn’t work on my machine. So, to avoid program termination this function was written. If you’re using COFFE on a machine that doesn’t have this problem you can comment this function in the code

coffe.utils.check_for_valid_path(path)

coffe.utils.check_hard_params(hard_params, run_options)

This function checks the hardblock/process parameters to make sure that all the parameters have been read in. Right now, this functions just checks really basic stuff like checking for unset values

coffe.utils.compare_tfall_trise(tfall, trise)

Compare tfall and trise and returns largest value or -1.0 -1.0 is return if something went wrong in SPICE

coffe.utils.create_output_dir(arch_file_name, arch_out_folder)

This function creates the architecture folder and returns its name. It also deletes the content of the folder in case it’s already created to avoid any errors in case of multiple runs on the same architecture file. If arch_out_folder is specified in the input params file, then that is used as the architecture folder, otherwise the folder containing the arch params file is used.

coffe.utils.extract_initial_tran_size(filename, use_tgate)

Parse the initial sizes file and load values into dictionary. Returns this dictionary.

coffe.utils.handle_error(fn, expected_vals: set = None)

coffe.utils.load_ptn_params(filename)

Parse the user defined partition settings, these get read into a dict for each partition in the design

coffe.utils.load_run_params(filename)

coffe.utils.parse_ptn_param_line(line)

coffe.utils.parse_yml_config(yaml_file: str) → dict

Takes in possibly unsafe path and returns a sanitized config

coffe.utils.print_and_write(file, string)

This function takes a file name and a string, it prints the string to the terminal and writes it to the file. Since this sequence is repeated a lot in the code this function is added to remove some redundent code. Note: the file should be open for writing before calling this function

coffe.utils.print_architecture_params(arch_params_dict, report_file_path)

coffe.utils.print_area_and_delay(report_file, fpga_inst)

Print area and delay per subcircuit

coffe.utils.print_block_area(report_file, fpga_inst)

Print physical area of important blocks (like SB, CB, LUT, etc.) in um^2

coffe.utils.print_error(value, argument, filename, msg='')

coffe.utils.print_error_not_compatable(value1, value2)

coffe.utils.print_hardblock_info(report_file, fpga_inst)

coffe.utils.print_power(report_file, fpga_inst)

Print power per subcircuit

coffe.utils.print_run_options(args, report_file_path)

This function prints the run options entered by the user when running COFFE, in the terminal and the report file

coffe.utils.print_summary(arch_folder, fpga_inst, start_time)

coffe.utils.print_vpr_areas(report_file, fpga_inst)

coffe.utils.print_vpr_delays(report_file, fpga_inst)

coffe.utils.sanatize_str_input_to_list(value)

Makes sure unneeded quotes arent included when a string of values is seperated by a space and saved into string seperated by spaces and surrouneded with quotes

coffe.utils.sanitize_config(config_dict) → dict

Modifies values of yaml config file to do the following: - Expand relative paths to absolute paths

coffe.utils.use_initial_tran_size(initial_sizes, fpga_inst, tran_sizing, use_tgate)

coffe.vpr module

coffe.vpr.print_vpr_file(fpga_inst, arch_folder, enable_bram_module)

coffe.vpr.print_vpr_file_flut_hard(vpr_file, fpga_inst)

coffe.vpr.print_vpr_file_memory(vpr_file, fpga_inst)

Module contents