What is RAD-Gen and what can it do?

ASIC-DSE Features & Use Cases

Sweep RTL or VLSI design parameters

If a user wanted to compare the performance of something like a Network-on-Chip across different target clock frequencies (or other VLSI parameters), or across different numbers of virtual channels (or other RTL parameters), they could use the ASIC-DSE subtool in RAD-Gen to perform a sweep of the RTL parameters and get PPA results for each configuration. This would allow the user to determine which configuration is best for their application or RAD Device.

  • Designers may want to take a design and get PPA results across a range of VLSI parameters such as target clock frequency, # metal Layers, standard cell utilization, etc. They may also want to try different configurations for their parameterizable RTL. For example a NoC can have a range of virtual channels, flit widths, or depth of buffers depending on the application.

  • RAD-Gen make above use case easier by creating a configuration file and executing a few commands.

SRAM “Compiler”: Creating SRAMs from existing Macros

  • There may be a case (as we found for ASAP7) in which a PDK has existing SRAM macros that are too small or have different numbers of ports than what a designer requires.

  • RAD-Gen’s quick and dirty solution to this problem is an SRAM mapper which inputs a user’s SRAM specification and an existing library of SRAMs, using bit cell utilization as the cost function, outputting a larger SRAM stitched together with appropriate muxing & decoding logic.

ASIC tool pre/post processing utilities

  • For each stage of the ASIC flow and subsequent post processing steps (such as GDS scaling) RAD-Gen outputs human readable & csv formatted outputs for easy integration / understanding of results

COFFE Features & Use Cases

COFFE is a tool which performs HSPICE driven automatic transistor sizing for FPGA circuitry. It can be used to get PPA estimates for a particular FPGA architecture. It does this by sizing transistors and optimizing PPA for the many custom circuitry that makes up an FPGA fabric. FPGA hardblocks can be evaluated by running them through the ASIC-DSE tool and then using COFFE to perform sizing on the custom logic which connects them to the programmable fabric.

If one wanted to evaluate an FPGA fabric on a new process technology (maybe the new ASAP5), they could use the COFFE subtool in RAD-Gen to perform automatic transistor sizing for the custom FPGA circuitry. Custom hardblocks such as BRAMs or DSPs or any user customized RTL can be included in the user defined FPGA fabric. The COFFE subtool will call the ASIC-DSE subtool to run the standard cell ASIC flow for RTL hardblocks. A classic evaluation that could be done would be to raise the question of what is the PPA of an FPGA at new process technology using either pass transistors or transmission gates, one could compare the PPA outputs of the two different FPGA fabrics and determine which is better for the new process technology.

IC-3D Features & Use Cases

RAD-Gen also includes tools which model 3D integrated circuits to be able to consider the effect of 3D on FPGA & RAD architectures. It includes automatic buffer chain generation using HSPICE to meet desired area / delay targets. PDN modeling is performed by using user IR drop targets to determine how many TSVs are required for a particular configuration. This estimates the area taken up in the base die.

If one wanted to be able to evaluate a RAD device or FPGA fabric which includes multiple dies using 3D integration, they would need to know a few things.

  1. How does the 3D Power Delivery Network (PDN) affect the area available for logic and routing for each die?

In 3D PDNs (depending on the type of bonding) often TSVs need to be put through the substrate of a die to deliver power, ground, and I/O signals going off chip. These TSVs act as holes in the substrate in which transistors cannot be placed, they can be thought of as a “swiss cheese”. To know how many and where these “swiss cheese” holes are we need to try to estimate the amount of holes required to meet the IR drop targets of the RAD/FPGA device.

  1. How large should the driver circuits be to communicate between dies?

Dies can be connected through solder microbumps, hybrid bonding, or a combination of them and TSVs (depending on if using Face-to-Back, Face-to-Face, etc bonding). To be able to understand the timing, power, and area cost of these connections we would want to perform design space exploration on these drivers while they drive the inter-die connections.

With the IC-3D subtool in RAD-Gen we can perform both of these tasks, and be able to evaluate 3D RAD/FPGA devices. We can also create floorplans respecting the “swiss cheese” holes and enabling easier integration of our new 3D device into something like VTR for 3D CAD-tool evaluations.

  • Die-to-die modeling by iteratively finding buffer chains to meet PPA targets w.r.t the driver load, defined by the 3D intergration process and packaging.

  • PDN modeling to get IR drop estimates and area taken up by TSVs