RAD Gen
  • RAD-Gen Quick Start Guide
    • What is RAD-Gen and what can it do?
      • ASIC-DSE Features & Use Cases
        • Sweep RTL or VLSI design parameters
        • SRAM “Compiler”: Creating SRAMs from existing Macros
        • ASIC tool pre/post processing utilities
      • COFFE Features & Use Cases
      • IC-3D Features & Use Cases
    • Installation and Setup
      • Clone Repository
      • Python Setup and Activation
      • ASAP7 PDK Setup
      • RAD-Gen ASIC Flow ASAP7 Specific Dependencies
    • Examples (How to Run)
      • ALU ASIC Flow Example
        • ALU Clock Frequency Sweep
        • ALU Hammer ASIC Flow
      • SRAM Generator Example
        • SRAM Single Macro ASIC Flow
        • SRAM Stitched Macro ASIC Flow
      • Network-on-Chip (NoC) RTL Parameter Sweep Example
        • NoC RTL Parameter Sweep
        • NoC RTL Sweep Point ASIC Flow
      • COFFE Stratix IV FPGA Fabric Example
        • Parsing Stratix IV RRG
        • Running Stratix IV through COFFE Flow
  • Common Functionality
    • Data Structures
      • Top Level
      • CLI / Structs / Tool Invocation
      • Current Existing Mappings
      • Format of CLI args, structs, and config file(s)
      • Hierarchically Defined Parameters
      • Initialization
        • Top Level Priority Order
        • Single Field Example
        • Init Function Walkthrough
        • Internal Init Priority Order
    • Testing
      • Usage
      • Code Structure
        • Top Level Python Files
        • Per-test Directory Structure
      • Updating Golden Results
      • Configuration Initialization
        • Test Standards
      • Parsing
        • Test Standards
      • ALU VLSI Sweep + Stdcell ASIC Flow
        • Golden Results
      • SRAM Generation + Stdcell ASIC Flow
        • Golden Results
      • NoC RTL Sweep + Stdcell ASIC Flow
        • Golden Results
  • ASIC-DSE Subtool
    • ASIC-DSE Overview
    • Modes of Operation
      • ASIC Flow
        • ASIC-DSE Environment Config
        • Flow Configs
  • IC-3D Subtool
    • IC-3D Overview
    • RC Value Generation
    • Bibliography
  • COFFE Subtool
    • COFFE Overview
      • COFFE Configuration File Parameter Descriptions
        • Utility Parameters
        • FPGA Architecture Parameters
        • Memory Block Parameters
        • Additional Tx Sizing (Custom Circuit Flow) Parameters
        • Hardblock Parameters
  • RAD-Gen API
    • asic_dse package
      • Submodules
      • asic_dse.asic_dse module
      • asic_dse.custom_flow module
      • asic_dse.hammer_flow module
      • asic_dse.sram_compiler module
      • Module contents
    • coffe package
      • Submodules
      • coffe.basic_subcircuits module
        • RAM_tgate_generate()
        • RAM_tgate_generate_lp()
        • inverter_generate()
        • lvl_shifter_generate()
        • nand2_generate()
        • nand2_generate_lp()
        • nand3_generate()
        • nand3_generate_lp()
        • ptran_generate()
        • ptran_pmos_generate()
        • rest_generate()
        • tgate_generate()
        • tgate_generate_lp()
        • wire_generate()
      • coffe.ble module
      • coffe.carry_chain module
      • coffe.cb_mux module
      • coffe.circuit_baseclasses module
      • coffe.coffe module
      • coffe.constants module
      • coffe.cost module
        • cost_function()
        • get_eval_area()
      • coffe.data_structs module
      • coffe.debug module
      • coffe.ff_subcircuits module
        • generate_ptran_2_input_select_d_ff()
        • generate_ptran_d_ff()
        • generate_tgate_2_input_select_d_ff()
        • generate_tgate_d_ff()
      • coffe.fpga module
      • coffe.gen_routing_loads module
      • coffe.hardblock module
      • coffe.load_subcircuits module
        • RAM_local_routing_load_generate()
        • general_routing_load_generate()
        • hb_local_routing_load_generate()
        • local_routing_load_generate()
      • coffe.logic_block module
      • coffe.lut module
      • coffe.lut_subcircuits module
        • generate_carry_chain_perf_ripple()
        • generate_carry_inter()
        • generate_full_adder()
        • generate_full_adder_simplified()
        • generate_ptran_lut4()
        • generate_ptran_lut5()
        • generate_ptran_lut6()
        • generate_ptran_lut_driver()
        • generate_ptran_lut_driver_load()
        • generate_ptran_lut_not_driver()
        • generate_skip_and_tree()
        • generate_tgate_lut4()
        • generate_tgate_lut5()
        • generate_tgate_lut6()
        • generate_tgate_lut_driver()
        • generate_tgate_lut_driver_load()
        • generate_tgate_lut_not_driver()
      • coffe.memory_subcircuits module
        • generate_columndecoder()
        • generate_columndecoder_lp()
        • generate_configurabledecoder2ii()
        • generate_configurabledecoder2ii_lp()
        • generate_configurabledecoder3ii()
        • generate_configurabledecoder3ii_lp()
        • generate_configurabledecoderi()
        • generate_configurabledecoderi_lp()
        • generate_configurabledecoderiii()
        • generate_configurabledecoderiii_lp()
        • generate_level_shifter()
        • generate_memorycell()
        • generate_memorycell_lp()
        • generate_mtj_cs_lp()
        • generate_mtj_memorycell_high_lp()
        • generate_mtj_memorycell_low_lp()
        • generate_mtj_memorycell_reference_lp()
        • generate_mtj_memorycell_reference_lp_target()
        • generate_mtj_memorycellh_reference_lp()
        • generate_mtj_sa_lp()
        • generate_mtj_writedriver_lp()
        • generate_pgateoutputcrossbar()
        • generate_precharge()
        • generate_precharge_lp()
        • generate_rowdecoderstage0()
        • generate_rowdecoderstage0_lp()
        • generate_rowdecoderstage1()
        • generate_rowdecoderstage1_lp()
        • generate_rowdecoderstage3()
        • generate_rowdecoderstage3_lp()
        • generate_samp()
        • generate_samp_lp()
        • generate_wordline_driver()
        • generate_wordline_driver_lp()
        • generate_writedriver()
        • generate_writedriver_lp()
      • coffe.mux module
      • coffe.mux_subcircuits module
        • generate_dedicated_driver()
        • generate_ptran_2_to_1_mux()
        • generate_ptran_2lvl_mux()
        • generate_ptran_2lvl_mux_no_driver()
        • generate_tgate_2_to_1_mux()
        • generate_tgate_2lvl_mux()
        • generate_tgate_2lvl_mux_no_driver()
      • coffe.new_ram module
      • coffe.parsing module
      • coffe.plotting module
      • coffe.ram module
      • coffe.sb_mux module
      • coffe.spice module
      • coffe.top_level module
        • generate_HB_local_mux_top()
        • generate_RAM_local_mux_top()
        • generate_RAM_local_mux_top_lp()
        • generate_columndecoder_top()
        • generate_columndecoder_top_lp()
        • generate_configurabledecoder2ii_top()
        • generate_configurabledecoder2ii_top_lp()
        • generate_configurabledecoderi_top()
        • generate_configurabledecoderi_top_lp()
        • generate_configurabledecoderiii_top()
        • generate_configurabledecoderiii_top_lp()
        • generate_dedicated_driver_top()
        • generate_flut_mux_top()
        • generate_general_ble_output_top()
        • generate_local_ble_output_top()
        • generate_lut4_top()
        • generate_lut5_top()
        • generate_lut6_top()
        • generate_lut_and_driver_top()
        • generate_lut_driver_not_top()
        • generate_lut_driver_top()
        • generate_mtj_charge()
        • generate_mtj_discharge()
        • generate_mtj_read_power_top_lp()
        • generate_mtj_sa_top()
        • generate_mtj_write_power_top_lp()
        • generate_pgateoutputcrossbar_top()
        • generate_precharge_top()
        • generate_precharge_top_lp()
        • generate_rowdecoderstage0_top()
        • generate_rowdecoderstage0_top_lp()
        • generate_rowdecoderstage1_top()
        • generate_rowdecoderstage1_top_lp()
        • generate_rowdecoderstage3_top()
        • generate_rowdecoderstage3_top_lp()
        • generate_samp_top()
        • generate_samp_top_part1()
        • generate_samp_top_part1_lp()
        • generate_samp_top_part2()
        • generate_samp_top_part2_lp()
        • generate_sram_read_power_top()
        • generate_sram_read_power_top_lp()
        • generate_sram_writehh_power_top_lp()
        • generate_sram_writelh_power_top_lp()
        • generate_sram_writep_power_top_lp()
        • generate_wordline_driver_top_lp()
        • generate_writedriver_top()
        • generate_writedriver_top_lp()
      • coffe.tran_sizing module
      • coffe.utils module
        • check_arch_params()
        • check_for_time()
        • check_for_valid_path()
        • check_hard_params()
        • compare_tfall_trise()
        • create_output_dir()
        • extract_initial_tran_size()
        • handle_error()
        • load_ptn_params()
        • load_run_params()
        • parse_ptn_param_line()
        • parse_yml_config()
        • print_and_write()
        • print_architecture_params()
        • print_area_and_delay()
        • print_block_area()
        • print_error()
        • print_error_not_compatable()
        • print_hardblock_info()
        • print_power()
        • print_run_options()
        • print_summary()
        • print_vpr_areas()
        • print_vpr_delays()
        • sanatize_str_input_to_list()
        • sanitize_config()
        • use_initial_tran_size()
      • coffe.vpr module
        • print_vpr_file()
        • print_vpr_file_flut_hard()
        • print_vpr_file_memory()
      • Module contents
    • common package
      • Submodules
      • common.constants module
      • common.data_structs module
      • common.gds_fns module
        • asap7_scale_gds()
        • get_area()
        • main()
      • common.new_data_structs module
      • common.rr_parse module
      • common.spice_parser module
      • common.utils module
      • Module contents
    • ic_3d package
      • Submodules
      • ic_3d.buffer_dse module
      • ic_3d.ic_3d module
      • ic_3d.pdn_modeling module
      • ic_3d.sens_study_plot module
      • Module contents
    • rad_gen package
      • Submodules
      • rad_gen.main module
      • Module contents
  • Code Structure
    • Overview
    • Submodules
    • Data structures, initialization, and utilities: common
    • ASIC flow + SRAM compiler: ASIC-DSE
    • FPGA circuit level DSE + transistor sizing: COFFE
    • 3D Die-to-die connections + PDN modeling: IC-3D
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